Arjun Suresh (talk | contribs) (Created page with "Consider a system with a two-level paging scheme in which a regular memory access takes 150 nanoseconds, and servicing a page fault takes 8 milliseconds. An average instructio...") |
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(A) 645 nanoseconds | (A) 645 nanoseconds | ||
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(B) 1050 nanoseconds | (B) 1050 nanoseconds | ||
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(C) 1215 nanoseconds | (C) 1215 nanoseconds | ||
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'''(D) 1230 nanoseconds''' | '''(D) 1230 nanoseconds''' | ||
Consider a system with a two-level paging scheme in which a regular memory access takes 150 nanoseconds, and servicing a page fault takes 8 milliseconds. An average instruction takes 100 nanoseconds of CPU time, and two memory accesses. The TLB hit ratio is 90%, and the page fault rate is one in every 10,000 instructions. What is the effective average instruction execution time?
(A) 645 nanoseconds
(B) 1050 nanoseconds
(C) 1215 nanoseconds
(D) 1230 nanoseconds
Consider a system with a two-level paging scheme in which a regular memory access takes 150 nanoseconds, and servicing a page fault takes 8 milliseconds. An average instruction takes 100 nanoseconds of CPU time, and two memory accesses. The TLB hit ratio is 90%, and the page fault rate is one in every 10,000 instructions. What is the effective average instruction execution time?
(A) 645 nanoseconds
(B) 1050 nanoseconds
(C) 1215 nanoseconds
(D) 1230 nanoseconds
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